The present invention relates to semiconductor devices and magnetic random access memories (MRAMs), more particularly, to magnetic memory cells of the magnetic domain wall motion type.
Recently, the MRAM, which uses magnetoresistance effect elements as memory cells, has been proposed as one of non-volatile memories, which are a sort of semiconductor devices. Especially, magnetoresistance effect elements having a magnetic tunnel junction (which may be referred to as “MTJ”, hereinafter) are often used as MRAM memory cells due to the advantage of a very large magnetoresistance effect. The magnetic tunnel junction has a laminated structure in which a non-magnetic dielectric film (hereinafter, referred to as tunnel barrier film) is disposed between two ferromagnetic films. Data are stored as the relative direction of the magnetizations of the two ferromagnetic films. For example, the state in which the magnetizations are directed in parallel is correlated with data “0” and the state in which the magnetizations are directed in antiparallel is correlated with data “1”. The electric resistance for a current flowing in the perpendicular direction to the film surface of the laminated structure varies depending on the relative angle of the magnetizations of the two ferromagnetic films. The electric resistance of the magnetic tunnel junction takes the minimum value when the magnetizations are directed in parallel, and takes the maximum value when the magnetizations are directed in antiparallel. The data read is achieved by using the changes in the electric resistance. The MRAM attracts a lot of attention in the field of embedded memories, and there is a demand for the high-speed random access of the MRAM as replacements of SRAMs (static random access memory) and DRAMs (dynamic random access memory).
Various MRAMs are known in the art and one type of the MRAM is the magnetic domain wall motion type. The magnetic domain wall motion type MRAM achieves data writing by moving the magnetic domain wall through the spin transfer effect of spin-polarized electrons with a write current flowing in the in-plane direction of a ferromagnetic film and thereby directing the magnetization of the ferromagnetic film in the direction depending on the direction of the write current. Such a magnetic domain wall motion type MRAM is disclosed in 2009 Symposium on VLSI Technology Digest of Technical Papers 12A-2.
FIG. 1A is a diagram schematically showing the structure of a memory cell 300 of the magnetic domain wall motion type MRAM disclosed in this document. The memory cell shown in FIG. 1A includes a magnetoresistance effect element 1 and NMOS transistors 51 and 52. The magnetoresistance effect element 1 includes: magnetization fixed layers 11, 12; a magnetic recording layer 2 disposed on the magnetization fixed layers 11, 12; a reference layer 4; and a tunnel barrier layer 3 disposed between the magnetic recording layer 2 and the reference layer 4. The magnetization fixed layers 11, 12 and the reference layer 4 are each formed of a ferromagnetic film having a fixed magnetization. The magnetic recording layer 2 is also formed of a ferromagnetic film. The magnetizations of regions 2a and 2b of the magnetic recording layer 2, which are coupled with the magnetization fixed layers 11 and 12, respectively, are fixed by the exchange coupling with the magnetization fixed layers 11 and 12. Hereinafter, the regions 2a and 2b may be referred to as magnetization fixed regions 2a and 2b, respectively. The region 2c between the magnetization fixed regions 2a and 2b has a reversible magnetization. Hereinafter, the region 2c may be referred to as magnetization reversible region 2c. The reference layer 4, the tunnel barrier layer 3 and the magnetization reversible region 2c form an MTJ.
The NMOS transistor 51 has a drain connected to the magnetization fixed layer 11 and a source connected to a write bitline BL1. The NMOS transistor 52 has a drain connected to the magnetization fixed layer 12 and a source connected to a write bitline BL2. The gates of the NMOS transistors 51 and 52 are commonly connected to the word line WL. In the structure shown in FIG. 1A, the reference layer 4 is connected to the grounding line GND. In FIG. 1A, the arrows 101, 102, 110 and 120 indicate the directions of the magnetizations of the respective layers.
FIG. 2A is a cross section view showing an example of the cross section structure of the memory cell 300 shown in FIG. 1A and FIG. 3A is a plan view showing an example of the layout of the memory cell 300. FIG. 2A schematically shows the NMOS transistors 51 and 52, because the diffusion layers of the NMOS transistors 51 and 52 are actually disposed to extend in the direction parallel to the write bitlines BL1 and BL2.
As shown in FIG. 2A, the tunnel barrier film 3 and the reference layer 4 are sequentially laminated on the magnetic recording layer 2 to form an MTJ. The magnetization fixed layers 11 and 12 are disposed in contact with the bottom surface of the magnetic recording layer 2 near both ends of the magnetic recording layer 2. The reference layer 4 is connected to a grounding line GND via a via-contact 8. The drain 51a of the NMOS transistor 51 is connected to the magnetization fixed layer 11 via a via-contact 61, and the drain 52a of the NMOS transistor 52 is connected to the magnetization fixed layer 12 via a via-contact 62. The grounding line GND is formed of a metal interconnection located in a first interconnection layer. The bitlines BL1 and BL2 are, on the other hand, formed of a metal interconnection located in a second interconnection layer which is positioned above the first interconnection layer.
As shown in FIG. 3A, each word line WL is provided in the form of a polysilicon gate and disposed to intersect diffusion layers 53 and 54. Each NMOS transistor 51 is formed by a word line WL and a diffusion layer 53, and each NMOS transistor 52 is formed by a word line WL and a diffusion layer 54. The sources of the NMOS transistors 51 and 52 are connected to the write bitlines BL1 and BL2 via via-contacts 63 and 64. The reference layer 4 is connected to the grounding line GND via the via-contact 8. The grounding lines GND are disposed in parallel to the word line WLs.
The data writing into the memory cell 300 shown in FIGS. 1A to 3A is achieved by generating a write current flowing between the write bitlines BL1 and BL2 with the NMOS transistors 51 and 52 turned on, and thereby switching the magnetization direction 110 of the magnetization reversible region 2c of the magnetic recording layer 2. The data reading is, on the other hand, achieved by generating a read current flowing from the write bitline BL1 (or BL2) to the grounding line GND via the MTJ of the magnetoresistance effect element 1 and comparing the read current with a reference current by a sense amplifier (not shown). The ground line GND is shared over the memory array.
Although FIGS. 1A to 3A shows that the reference layer 4 is connected to the grounding line GND in the memory cell 300, the reference layer 4 may be connected to a read bitline RBL, which is individually provided for each column, in place of the grounding line GND. FIGS. 1B to 3B show such a structure in which the reference layer 4 is connected to a read bitline RBL. In detail, FIG. 1B schematically shows the structure of the memory cell 300 in which the reference layer 4 is connected to the read bitline RBL, and FIG. 2B is a cross section view showing an example of the cross section structure of the MRAM cell shown in FIG. 1B. FIG. 3B is a layout diagram showing an example of the layout of the MRAM cell shown in FIG. 1B. The high-speed read from an MRAM memory cell requires reduction in the capacitance of the interconnection used for data read, and the structure shown in FIGS. 1B to 3B, in which a read bitline RBL is provided for each column, is suitable for the high-speed operation. As shown in FIGS. 2B and 3B, the read bitlines RBL are disposed in parallel to the write bitlines BL1 and BL2. In the structure shown in FIG. 2B, in which the read bitlines RBL do not intersect with the write bitlines BL1 and BL2, the read bitlines RBL are formed of a metal interconnection located in the first interconnection layer. Except for this point, the memory cell 300 shown in FIGS. 1B to 3B has the same structure as that shown in FIGS. 1A to 3A.
FIG. 4 is a block diagram showing one example of the structure of an MRAM which incorporates memory cells 300 shown in FIGS. 1B to 3B. The MRAM shown in FIG. 4 includes a memory cell array in which memory cells 300 structured as described above are arranged in rows and columns. The memory cell array further includes word lines WL, write bitlines BL1, BL2 and read bitlines RBL.
The MRAM further includes an X selector 301, a write Y selector 302, a write current supply circuit 303, a read Y selector 304, a read current load circuit 305, a sense amplifier 306, an output circuit 307 and a reference current circuit 308. The X selector 301 is connected to the word lines WL, and selects the word line WL connected to the selected memory cell (the memory cell 300 to be accessed) in the write operation and read operation. In FIG. 4, the selected memory cell is denoted by the numeral 300s and the selected word line is denoted by the numeral WLs.
The write Y selector 302 is connected to the write bitlines BL1 and BL2, and selects the write bitlines BL1 and BL2 connected to the selected memory cell 300s as the selected write bitlines BL1s and BL2s. The write current supply circuit 303 generates a write current to be fed to the selected memory cell 300s in response to data inputted to the inputs of the write current supply circuit 303.
The read Y selector 304 is connected to the read bitlines RBL. The read Y selector 304 selects the read bitline RBL connected to the selected memory cell 300s as the selected read bitline RBLs. The read current load circuit 305 applies a predetermined voltage to the selected read bitline RBLs. The reference current circuit 308 includes a constant current circuit or reference cells which have the same structure as the memory cells. The sense amplifier 306 compares the read current flowing through the selected read bitline RBLs with a reference current supplied from the reference current circuit 308 to identify data stored in the selected memory cell 300s. The output circuit 307 outputs the data identified by the sense amplifier 306.
The above-described MRAM suffers from a problem of reduction in the read margin caused by the variability in the MR ratio of the MTJ on the manufacturing processes. In the above-described MRAM, the read current flowing through the MTJ of the selected memory cell 300s is compared with the reference current iREF to identify the data stored in the selected memory cell 300s. The ratio of the read current iH of the selected memory cell 300s for the MTJ in the high-resistance state to the read current iL for the MTJ in the low-resistance state depends on the MR ratio of the MTJ. FIG. 5 is a graph showing an exemplary waveform of the read current. The sense amplifier 306 identifies the data by using the differential current ΔH having the current level of the difference between the read current iH and the reference current iREF or the differential current ΔL having the current level of the difference between the read current iL and the reference current iREF. According to a reference in the art, a typical MR ratio of an MTJ is 44%. In this case, the ratio of the read currents iL and iH is represented by expression (1):iL:iH≈1.44:1.  (1)
In general, the reference current iREF is generated so as to have the average value of the read current iH for the high-resistance state and the read current iL for the low-resistance state. The reference current iREF normalized by the read current iH for the high-resistance state is represented by expression (2):iREF=(1.44+1)/2≈1.22.  (2)
Accordingly, the ratio of the read current iH for the high-resistance state to the reference current iREF is represented by expression (3) and the ratio of the reference current iREF to the read current iL for the low-resistance state is represented by expression (4):iH:iREF=1:1.22≈0.82:1, and  (3)iREF:iL=1.22:1.44≈1:1.18.  (4)The differential currents ΔL and ΔH which are available for the sense amplifier 306 in the events that the MTJ of the selected memory cell 300s is placed in the low-resistance state and the high-resistance state, respectively, can be represented by the following expressions, which are derived from expressions (1) to (4):
                                                                                          Δ                  ⁢                                                                          ⁢                  L                                =                                ⁢                                                                            i                      L                                        -                                          i                      REF                                                        =                                                            1.18                      ×                                              i                        REF                                                              -                                          i                      REF                                                                                  ,                                                                                          =                                ⁢                                  0.18                  ×                                      i                    REF                                                              ,              and                                                          (        5        )                                                                                                      Δ                  ⁢                                                                          ⁢                  H                                =                                ⁢                                                                            i                      REF                                        -                                          i                      H                                                        =                                                            i                      REF                                        -                                          0.82                      ·                                              i                        REF                                                                                                        ,                                                                          =                            ⁢                              0.18                ×                                                      i                    REF                                    .                                                                                        (        6        )            
Expressions (7) and (8) which represent the differential currents ΔL and ΔH with the current iH, which is the read current for the high-resistance state, can be obtained from expressions (5) and (6), respectively, as follows:ΔL=0.18×iH/0.82≈0.22×iH.  (7)ΔH=0.18×iH/0.82≈0.22×iH.  (8)As is understood from expressions (7) and (8), only 22% of the read current iH is available as the differential currents ΔL and ΔH, which is fed to the sense amplifier 306, for the MR ratio of 44%. This undesirably reduces the read margin when the MR ratio is decreased due to the variability on the manufacturing processes.
It should be noted that techniques for increasing the read margin are disclosed in Japanese Patent Application Publications Nos. 2008-047669, 2007-004969, 2006-185477, 2004-103212, and 2004-046962. According to a study of the inventor, however, there is a more advantageous approach as discussed below.